The inventive concept relates generally to semiconductor memory devices including a variable resistance memory and operating methods for same.
Semiconductor memory devices may be classified as volatile or nonvolatile according to their operative nature. Volatile memory devices—including static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and the like—lose stored data in the absence of applied power. In contrast, nonvolatile memory devices are able to retain stored data in the absence of applied power. Nonvolatile memory devices include certain read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), and the like.
Emerging (or so-called “next generation”) nonvolatile memory technologies offer many design and performance advantages. One example of next generation nonvolatile memory devices is the Spin Transfer Resistive Random Access Memory or STT-MRAM. The STT-MRAM uses a variable memory cell resistance to indicate a stored data value. The variable resistance of MRAM memory cells may be “written” by the application of a defined set of magnetic or electric conditions to the memory cell. For example, an STT-MRAM memory cell includes a magnetic tunnel junction (MTJ) that in certain embodiments includes a magnetically “pinned” material layer and a magnetically “free” material layer. The resistance value exhibited by the STT-MRAM memory cell is a function of the magnetization direction(s) of these two material layers.
That is, the magnetization direction of the free layer may be changed by electrical and/or magnetic factors, conditions and/or influences internal to the MRAM memory cell and/or externally applied to the MRAM memory cell. As a result, certain external magnetic fields, perhaps unintentionally applied to a MRAM memory cell, may cause a undesired change in the resistance of the MRAM memory cell. Such inadvertent changes in one or more MRAM memory cell resistances may subsequently result in stored data errors.